1. Field of the Invention
The present invention relates to thin-film transistor (TFT) video processing circuits, and more particularly, the present invention discloses a level shifter circuit that uses a bootstrap circuit to decrease power consumption and decrease shifting time.
2. Description of the Prior Art
Logic circuitry for the LCD display typically comprises a vertical shift register and a level shifter. The vertical shift register enables one column of pixels at a time in succession. The level shifter increases a voltage range of a signal from the vertical shift register. For example, the level shifter may take an input ranging from 0V to 10V and convert the input to an output ranging from −5V to 10V. Please refer to FIG. 1, which shows a level shifter according to the prior art. The level shifter 10 comprises a first transistor M1 and a second transistor M2. The second transistor M2 is a diode-connected transistor. In this example, the first transistor M1 and the second transistor M2 are both p-type metal-oxide-semiconductor (PMOS) transistors. The input to the level shifter 10 is at a gate of the first transistor M1, and the level shifter 10 is powered by a 15V bias voltage source comprising an upper voltage bias VDD (10V) and a lower bias voltage VEE (−5V). When the input is 0V, the first transistor M1 turns on, and the output becomes approximately 10V. When the input is 10V, the first transistor M1 turns off, and a current flowing in the second transistor M2 begins to pull the output voltage down. To maintain the current flowing in the second transistor M2, a source-gate voltage Vsg must be greater than a threshold voltage Vth of the second transistor M2. Because the gate of the second transistor M2 is coupled to the lower bias voltage VEE, the output will never drop below a low output voltage VEE+Vth. This presents three disadvantages to the prior art architecture. First, the output cannot be pulled fully to the lower bias voltage VEE. In other words, the output has a limited range from the upper bias voltage VDD to the low output voltage VEE+Vth. Second, because the low output voltage is dependent on the threshold voltage Vth of the second transistor M2, process variation will make the low output voltage inconsistent. Third, because the second transistor M2 is diode-connected, the second transistor M2 is always on, which wastes power.